In methods of manufacturing vertical memory devices, an insulation layer and a sacrificial layer may be alternately and repeatedly formed on a substrate. Holes may be formed through the insulation layers and the sacrificial layers. Channels may be formed to fill the holes. Openings may be formed through the insulation layers and the sacrificial layers. The sacrificial layers exposed by the openings may be removed to form gaps exposing the channels. ONO layers and gate structures including gate electrodes may be formed to fill the gaps.
The holes may have a high aspect ratio and may be arranged at a small distance, relatively. Problems of forming the holes unevenly or deforming the formed holes may occur.